The Road to RISC-V Summit: CAST to Highlight 32-bit Solutions in Functional Safety and Ultra-Low Power Ali Guerra | usagoldmines.com

October 18, 2024

Weblog

Picture Credit score: CAST

Throughout this 12 months’s RISC-V Summit, CAST can be in sales space S13 demonstrating its processors supplied in ASICs or FPGAs for embedded programs, Web of Issues edge gadgets, industrial management programs, automotive, and aerospace purposes. CAST’s RISC-V IP core line options processors targeted on aggressive 32-bit options in Practical Security and Extremely-Low Energy.

The EMSA5-FS 32-bit Embedded RISC-V Practical Security Processor is an ISO26262 ASIL D Prepared IP core that gives:

Single-issue, in-order, 5-stage pipeline processor with an non-obligatory L0 instruction cache
In depth RV32 base integer or base embedded ISA choices, together with full, partial, or non-obligatory help for RV32[I/E][C][M][F][D][A][Zicsr][Zifencei] and Vector Directions
Fail-safe design options, together with Twin Modular
Redundancy (DMR) in Lockstep or triple (TMR), Error Correcting Code (ECC), and pattern Reset and Security Supervisor modules
A whole ISO 26262 Certification Bundle, together with a Security Guide (SAM) and a Failure Modes, Results and Diagnostics Evaluation (FMEDA) doc

The efficiency and useful resource necessities of the EMSA5-FS fluctuate with its configuration and ASIC or FPGA implementation. DMR variations begin at 40k gates, and TMR at 60k. EMSA5-FS efficiency can surpass frequencies over 1GHz on superior processor nodes.

CAST’s 32-bit RISC-V low-power processors for embedded purposes require a small silicon footprint for minimal leakage and dynamic CPU energy. In addition they make use of superior energy administration methods akin to dynamic clock gating and clock frequency scaling. RISC-V help contains RV32 base integer or base embedded ISA and extensions, together with full, partial, or non-obligatory help for RV32[I/E][C][M][F][D][A][N][Zicsr][Zifencei] and Vector Directions.

For extra info, go to cast-inc.com/processors/risc-v.