By Nermeen Nabil Khear
December 31, 2024
Weblog
The microcontroller is a exceptional workhorse of embedded electronics, the closest that design engineers need to a ‘do every thing’ part. There are limits, nonetheless, even to the vary of features that an MCU can tackle: motor management is a type of functions which stretches the capabilities even of high-end MCUs.
That is an inherent characteristic of the MCU, which executes threaded directions in sequence; motor management requires deterministic management of each motor place/pace and motor present in real-time. Because of this, a low-end MCU alone can typically solely management a single servo motor.
For functions calling for the management of a number of servo motors, an FPGA can present a extra applicable {hardware} atmosphere due to its potential to execute two or extra time-critical features concurrently in parallel.
The industrial choices on the FPGA market, nonetheless, have previously put the designer in a dilemma: when implementing a demanding motor system design, OEMs have a robust choice for a single-chip resolution, however the type of FPGA which might run place, pace, and present management routines concurrently is on the high-density finish of the vary – and these high-end FPGAs are each giant and costly.
In multi-motor designs, a single MCU presents inadequate efficiency, whereas a single high-end FPGA gives ample efficiency however at a excessive value.
New developments within the low-density FPGA market at the moment are, nonetheless, providing a method for design engineers to sq. the circle, and to comprehend an inexpensive, single-chip resolution to the issue of controlling a number of servo motors.
Assorted Approaches to Bringing the MCU Contained in the FPGA
Confronted with the excessive value of implementing a single-chip motor management system primarily based on a high-end FPGA, designers have usually resorted to a two-chip strategy, combining an MCU with a small, low-density, inexpensive FPGA. On this structure (see Determine 1), the MCU usually handles the place and pace management perform, and the FPGA manages the present management loop and the interface to the motor’s place sensor (an encoder, Corridor sensor or optical place sensor).
Fig. 1: typical two-chip structure used for controlling a high-performance electrical motor
This two-chip resolution gives for deterministic management, however entails a tougher board structure, a extra advanced provide chain, and better bill-of-materials value than the equal single-chip resolution.
Producers of low-end and mid-range FPGAs have responded to this dilemma by bringing an MCU inside their merchandise, usually within the type of Arm® Cortex®-M MCU IP constructed into the FPGA. In some functions, the supply of an MCU core carried out in FPGA material can show very helpful, however for motor management routines, this soft-core MCU’s battle to offer the deterministic efficiency and timing which can be required. In a soft-core MCU implementation, the speed at which the management loop is up to date is often lowered, limiting such a single-FPGA resolution’s potential to keep up dependable and clean efficiency.
A New Hybrid Single-Chip Motor Answer
This has pushed the event of innovation on the low-density finish of the FPGA market: the GW5AS25 from GOWIN Semiconductor. This machine combines a 288MHz Arm Cortex-M4-based MCU, the AT32F437 from Artery, with an Arora-V FPGA containing 23,040 logic components in a single 256-pin package deal measuring 14mm x 14mm. The FPGA is fabricated in a low-power TSMC 22nm course of.
The GW5AS25’s system-in-package (SiP) configuration permits the motor system designer to partition system performance between the MCU performing place/pace management, and the FPGA operating the present management loops of 1 or two motors (see Determine 2).
Fig. 2: multi-motor management in a single chip
As Determine 2 exhibits, this resolution gives ample control-loop bandwidth to handle two motors working at excessive pace, but avoids the excessive value and measurement penalties incurred by way of a high-end FPGA to carry out the identical features.
This difficult-core MCU and FPGA SiP does greater than present a {hardware} platform for high-speed motor management: additionally it is supported by sources which assist to speed up the design of a single or twin everlasting magnet synchronous motor (PMSM). These embody:
- Reference design IP for implementing varied types of present loop management. Utilizing this IP, the designer can obtain PWM switching frequency in extra of 20kHz.
- Constructed-in assist for high-speed, real-time communication by way of an industrial Ethernet interface
As well as, encoder producers provide VHDL and Verilog code for the interface to their merchandise, simplifying their integration into an FPGA-based management system.
Single-Chip Answer Prepared for Analysis
Design engineers can experiment with the operation of the GW5AS25 by utilizing a growth package, the DK_MOTOR_GW5AS-EV25UG256_V1.0 (see Determine 3). This package features a present management loop IP, an encoder controller, an industrial Ethernet interface, an ADC carried out within the FPGA, place/pace management loops, and Ethernet stack carried out within the MCU.
Fig. 3: the DK_MOTOR_GW5AS-EV25UG256_V1.0 allows speedy growth of a multi-motor management system
This growth package demonstrates the feasibility of decreasing the fee, measurement, and complexity of a multi-motor system design by implementing a single-chip management resolution primarily based on an FPGA and hard-core MCU in a compact SiP.
This articles is written by : Nermeen Nabil Khear Abdelmalak
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